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Instruction set architecture
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71	THE FIRST ENTERPRISE CLASS 64-BIT ARMV8 SERVER: HP MOONSHOT SYSTEM’S HP PROLIANT M400 SERVER CARTRIDGE A PPLIED M ICRO X-G ENE -B ASED S ERVER D EMONSTRATES 35% L OW ER TCO S CALE -O UT W EB T IER /C ACHING E NVIRONMEN Add to Reading List Source URL: www.moorinsightsstrategy.com Language: English - Date: 2014-09-29 08:04:28 Applied Micro Circuits Corporation Power Architecture Instruction set architectures ProLiant ARM architecture Standard Performance Evaluation Corporation HP Integrated Lights-Out Hypervisor Windows NT 64-bit computing Hewlett-Packard Linaro
72	Advanced Parallel Architecture Lesson 2 Annalisa Massini Introduction Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-03-03 11:01:50 Parallel computing Central processing unit Microprocessors Instruction set architectures Classes of computers Bit-level parallelism Reduced instruction set computing Instruction-level parallelism 64-bit computing Instruction set Very long instruction word Microarchitecture
73	The Semantics of Power and ARM Multiprocessor Machine Code Jade Alglave2 Anthony Fox1 Samin Ishtiaq3 Magnus O. Myreen1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Central processing unit Computer architecture Computer memory Parallel computing Instruction set architectures Memory barrier Processor register Instruction set ARM architecture ALGOL 68 CPU cache Computer data storage
74	Contacts: Jim Ormond Add to Reading List Source URL: awards.acm.org Language: English - Date: 2016-05-18 11:44:53 Classes of computers Instruction set architectures Microprocessors Computer architecture Parallel computing EckertMauchly Award John Mauchly Complex instruction set computing Association for Computing Machinery Superscalar processor Computer X86
75	A hardware MP3 decoder with low precision floating point intermediate storage Andreas Ehliar, Johan Eilert LiTH-ISY-EXLink¨oping 2003 Add to Reading List Source URL: www.mp3-tech.org Language: English - Date: 2009-06-28 10:47:13 Computer arithmetic Central processing unit Computer architecture Processor register Instruction set Floating point Fixed-point arithmetic Decoder
76	Haifeng Niu Education -‐Current: Ph.D., Missouri University of Science and Technology, Rolla, US Add to Reading List Source URL: www.imscenter.net Language: English - Date: 2013-04-22 11:19:45 Instruction set architectures Automatic identification and data capture Privacy Radio-frequency identification Ubiquitous computing Wireless Robot ARM architecture Debugging Automation Texas Instruments TMS320
77	Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Instruction set architectures Computer memory X86 architecture X86-64 Java memory model X86 Memory barrier Spinlock Memory ordering Low-level programming language Itanium ARM architecture
78	Efficient SIMD Code Generation for Runtime Alignment and Length Conversion Peng Wu Alexandre E. Eichenberger Add to Reading List Source URL: researcher.watson.ibm.com Language: English - Date: 2009-10-23 16:02:22 Computer architecture Assembly languages Parallel computing Instruction set architectures Pointer Data structure alignment SIMD Offset Addressing mode DEC Alpha
79	T9000 - superscalar transputer Richard Forsyth Bob Krysiak Roger Shepherd INrvl0S Limited - SGS-Thomson Microelectronics Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:50 Central processing unit Stack machines Microprocessors Parallel computing Transputer Computer architecture Processor register CPU cache IDL Instruction set

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